The addressing of the data and coefficient memory or memories of DSP is of primary importance. For this reason, DSP include complex “automatic” address generation mechanisms that operate in parallel with mechanisms executing arithmetic operations. The addressing capabilities of the memories most typically used in current DSP rely on an address or index register, an offset register, and a modulo register. Thus a memory is addressed by means of an address register, and the value in the address register can be modified for each memory access by the value or values contained in the offset and/or modulo register(s).
Furthermore, DSP generally include two address generation systems that feed the arithmetic unit simultaneously and work with two separate memories. For example, two values can be multiplied and the result added to the value in an accumulator register by a call to only one program instruction.
However, this necessitates long instructions comprising a large number of bits, which makes the hardware costly.                Accordingly, an instruction must in particular specify:        the arithmetic operation to be executed,        in which register to place the result,        an addressing register appropriate for the memory,        the operation to be executed on the content of the addressing register,        the appropriate offset register,        the appropriate modulo register,        another addressing register appropriate for the memory,        the operation to be executed on the content of the other addressing register,        the offset register appropriate for the other addressing register, and        the modulo register appropriate for the other addressing register.        
To avoid excessively large instructions, the capabilities of DSP must be limited to strictly what is required to execute a particular number of specific algorithms, thus ruling out flexible use of DSP. For example, imposition of the following limitations has to be accepted:                small number of arithmetic operations,        small number of storage registers,        small number of addressing registers,        small number of operations on the addressing registers, and        fixed selection of the offset and modulo registers associated with the addressing register in a way that cannot be modified.        
An object of the invention is to provide a system for generating addresses that circumvents at least some of the limitations set out above and achieves flexibility in the choice of the algorithms that can be executed, using instructions much shorter than the instructions conventionally used in DSP.